As the integrated circuit (IC) technology makes rapid progress toward 100 nm gate transistors, the speed limiting factor is no longer the transistor delay, but the RC delay associated with the metal interconnects. A great deal of work is being done in this area on new and innovative materials and fabrication techniques to reduce the capacitance and thus reduce RC delay of interconnects. Currently studied low-k dielectrics include fluorinated silicon dioxide (SiO2), aerogels, and polymers. Additionally, as IC technology continues to scale, the aspect ratio of metal lines increases and the intra-level line-to-line capacitance increasingly dominates over the inter-level capacitance. Thus, it becomes increasingly important to implement low-k schemes between tightly spaced metal lines and less so between metal levels.
One approach to reducing the RC delay is provided in copending and commonly assigned application; attorney docket number 303.672US1, application Ser. No. 09/483881, entitled “Selective Electroless-Plated Copper Metallization,” which is hereby incorporated by reference. Further, an article by B. Shieh et al., entitled “Air-Gap Formation During IMD Deposition to Lower Interconnect Capacitance,” IEEE Electron Devices Letters, 19, no. 1, p. 16-18 (1998) presented simulations and some initial experimental results showing the possible capacitance reduction achievable using air-gap structures.
Another approach is described in an article by T. Ueda et al., entitled “A Novel Air Gap Integration Scheme for Multi-level Interconnects using Self-aligned Via Plugs,” 1998 Symposium on VLSI Technology, Digest of Technical Papers, p. 46-47 (1998) in which an air-gap structure was introduced between lines and SiO2 was provided between metal levels. As described in this article, an effective dielectric constant of 1.8 at 0.3 micrometer (μm) line spacing was obtained. The authors of this article used the combination of PE-CVD SiO2 with poor step coverage characteristics to intentionally form the air gaps, and biased HDP-CVD SiO2 with good filling capability for the formation of inter-metal dielectric (IMD). In another approach described by J. G. Fleming et al., entitled “Use of Air Gap Structures to Lower Intra-level Capacitance,” Proceedings of 1997 Dielectrics for ULSI Multi-level Interconnect Conference, p. 139 (1997) a process of fabricating air-gap structures to lower intra-level capacitance was introduced. The authors of this article used an oxide deposition process with poor step coverage to create the desired air gaps. Yet another approach is described in U.S. Pat. No. 5,900,668, by D. L. Wollesen, entitled “Low Capacitance Interconnection,” issued May 4, 1999, which describes a scheme in which the parasitic capacitance is reduced by removing sections of dielectric inter-layers by anisotropic etching to form air-gaps which can remain or be filled with another dielectric material with a lower dielectric constant. An example of a prior art multilevel metallization scheme according to this process is provided in FIG. 1.
Still, all of these approaches either involve complex additional processing steps or fail to provide an added benefit of reducing both intral-level line to line capacitance and the inter-level capacitance. Accordingly, there remains a need in the art to provide streamlined, improved methods and structures for alleviating the capacitance problems associated with via and metal line fabrication processes as design rules shrink.